Senior Memory Subsystem Verification Engineer
Listed on 2026-10-10
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Engineering
Test Engineer
Qualcomm Technologies, Inc. is seeking a motivated Design Verification Engineer to join its memory subsystem verification team.
You will develop verification strategies, build UVM-based test benches, and drive coverage closure for high-performance memory interfaces (LPDDR/DDR/HBM) and related PHY logic. The role emphasizes hands-on verification with Verilog, System Verilog, UVM, and SVA, spanning the full verification lifecycle from planning to regression and debug.
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This posting is for the Senior Memory Subsystem Verification Engineer role at QUALCOMM, Inc., based in Santa Clara, CA, United States.
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