Electrical Validation engineer Job Santa Clara area,California USA,Engineering

Need Hardware Engineers who have high-speed interface (DDR5/PCIe Gen
5) experience.
Candidates with Silicon Validation experience with Electrical background and Python scripting will be a plus.
Intel is okay for junior candidates with 3 to 5 years’ experience as well, but they should be strong in high-speed basics.
FPGA/Software/Functional Validation candidates are not relevant for this requirement.
Silicon validation experience, preferably in the area of SERDES, DDR or high-speed interface design.
Experience to validate PCIe, CXL, DDRx, LPDDR controller/chips for leading edge protocols and advanced nodes.
Understanding of JEDEC, PCIe Standard
Experience in PCIe TX/RX Validation
Knowledge on MRC algorithm and tuning for DDR memories
Bring up, characterization and validation of Silicon.
Experience in system marginality validation
Work with design team to debug problems and performance issues. Report results to design teams.
Support customer silicon bring up and post silicon queries of IP and help to debug customer issues with same.
Debug issues with SOC IP and boards as needed.
Execute test requests from design team or customers to measure specific parameters or root cause issues.
Recommend and pursue improvements to our test plan and environment to ensure the highest quality IP is produced and minimize any silicon issues
Good understanding of lab equipment and measurement techniques for high-speed interfaces. High speed scopes,probes, spectrum analyzers, BERTs.
Knowledge of board and package design, signal integrity and power integrity a plus
Knowledge of DDR trainings and memory system operation a plus
Software proficiency for python test scripting, data handling and reporting
Laboratory experience, including hands-on use of equipment: oscilloscope, logic analyzer, etc.
Excellent problem-solving skills, good communication skills and ability to work in a team environment
Work with design team to understand requirements, fashion tests and review results

Job Description

Need Hardware Engineers who have high-speed interface (DDR5/PCIe Gen
5) experience.
Candidates with Silicon Validation experience with Electrical background and Python scripting will be a plus.
Intel is okay for junior candidates with 3 to 5 years’ experience as well, but they should be strong in high-speed basics.
FPGA/Software/Functional Validation candidates are not relevant for this requirement.
Silicon validation experience, preferably in the area of SERDES, DDR or high-speed interface design.
Experience to validate PCIe, CXL, DDRx, LPDDR controller/chips for leading edge protocols and advanced nodes.
Understanding of JEDEC, PCIe Standard
Experience in PCIe TX/RX Validation
Knowledge on MRC algorithm and tuning for DDR memories
Bring up, characterization and validation of Silicon.
Experience in system marginality validation
Work with design team to debug problems and performance issues. Report results to design teams.
Support customer silicon bring up and post silicon queries of IP and help to debug customer issues with same.
Debug issues with SOC IP and boards as needed.
Execute test requests from design team or customers to measure specific parameters or root cause issues.
Recommend and pursue improvements to our test plan and environment to ensure the highest quality IP is produced and minimize any silicon issues
Good understanding of lab equipment and measurement techniques for high-speed interfaces. High speed scopes,probes, spectrum analyzers, BERTs.
Knowledge of board and package design, signal integrity and power integrity a plus
Knowledge of DDR trainings and memory system operation a plus
Software proficiency for python test scripting, data handling and reporting
Laboratory experience, including hands-on use of equipment: oscilloscope, logic…