Senior Circuit Timing Architect AI-Driven SoCs

NVIDIA seeks a Senior Circuit Timing Engineer to join our advanced hardware team in Santa Clara. You will drive timing analysis and signoff for digital, semi-custom, and analog macros, leveraging Nanotime, Prime Time, and Tempus while coordinating with PD, DFX, and Clocks groups.

The role emphasizes ECO-based timing fixes, low-power techniques, and an end-to-end silicon design flow from RTL to tape-out, with opportunities to apply AI/ML approaches during the design process.

We are currently recruiting a Senior Circuit Timing Architect for AI-Driven SoCs for our team in Santa Clara, CA, United States.

Our team is growing, and we are hiring a Senior Circuit Timing Architect for AI-Driven SoCs in Santa Clara, CA, United States.

This opening is for the Senior Circuit Timing Architect for AI-Driven SoCs role at NVIDIA.

We are seeking a motivated Senior Circuit Timing Architect for AI-Driven SoCs to join NVIDIA in Santa Clara, CA, United States.