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Hardware Physical Design Engineer
Job in
Santa Clara, Santa Clara County, California, 95053, USA
Listed on 2026-10-16
Listing for:
VIVA USA Inc
Full Time
position Listed on 2026-10-16
Job specializations:
-
Engineering
Electronics Engineer, Hardware Engineer, Automation & Mechatronics Engineer, Systems Engineer
Job Description & How to Apply Below
Senior Silicon Design Engineer
THE ROLE:This is a Physical Design Engineering role that will require to take the design from RTL to GDS with synthesis, Place n Route, timing, and Physical Verification
THE PERSON:Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams
RESPONSIBILTIES:- This engineer will work on leading edge technology nodes designs.
- This includes automated synthesis and timing driven place and route of RTL blocks for high speed Datapath and control logic applications, automated design flows for clock tree synthesis, clock gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
- You will also support floor planning, establishing design methodology, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.
- Major in EE, CS or related, master’s degree with 3+ years or Bachelor with 5+ years working experience, preferably with high designs or other high-performance IP designs.
- Experience in automated synthesis and timing driven place and route of RTL blocks (Verilog experience preferred) for high speed Datapath and control logic applications. Mainly in ICC2, fusion compiler, calibre and Prime Time.
- Experience in automated design flows for clock tree synthesis, clock gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction
- Strong background in digital circuit techniques, efficient and robust implementation topologies for logic functions, logic optimization, and transistor level circuit topologies for high speed, low power applications
- Major in EE, CS or related, master’s degree preferably with high-speed multi-gigabit Ser Des PHY designs or other high-performance IP designs.
- Onsite 5 days a week
VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status
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