Physical Design Engineer: RTL to GDS -Speed IP
Listed on 2026-10-16
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Engineering
Electronics Engineer, Hardware Engineer, Systems Engineer, Automation & Mechatronics Engineer
VIVA USA Inc. is seeking a Senior Silicon Design Engineer to drive RTL to GDS flows for high-speed datapath IP on site in Santa Clara, CA. You will lead automated synthesis, timing-driven place and route, CTS, clock gating, and power/area optimizations for advanced nodes.
Responsibilities include floor planning, design methodology, logic equivalence checks, and final IP signoff. Strong Verilog and multi-project coordination are essential for success.
We are seeking a motivated Physical Design Engineer: RTL to GDS for High-Speed IP to join VIVA USA Inc in Santa Clara, CA, United States.
For the Physical Design Engineer: RTL to GDS for High-Speed IP position at VIVA USA Inc, we are reviewing applications now.
Step into the Physical Design Engineer: RTL to GDS for High-Speed IP role at VIVA USA Inc in Santa Clara, CA, United States and grow with us.
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