DFT Engineer

5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs

Strong understanding of DFT fundamentals including cont rollability, observability, and scan-based testing

Proven expertise in ATPG pattern generation, analysis, and debug

Experience with MBIST, including memory test architectures and diagnostics

Knowledge of IO Test methodologies for interface and pin level validation

Solid understanding of clock DFT and clock verification concepts

Strong grasp of digital design and RTL fundamentals

Experience with industry standard DFT/ATPG EDA tools

Ability to work effectively in fast paced, high performance semiconductor programs

Strong analytical, problem solving, and communication skills

We are currently recruiting a DFT Engineer for our team in Santa Clara, CA, United States.

We have an opening for a DFT Engineer in Santa Clara, CA, United States within Engineering.

This role, DFT Engineer at AllianceIT Inc, could be your next move.