Design Verification Engineer – CPU Core Formal Verification

About Si Five

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer.

With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people’s lives; making the world a better place, one processor at a time.

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Job Description:

About the Role

SiFive is looking for a Staff Design Verification Engineer to drive formal verification of high-performance CPU core functionality.

This is a Staff individual-contributor role within the CPU Design Verification organization, focused on applying formal methods to complex out-of-order CPU core microarchitecture. The role is aimed at an engineer who can independently own difficult verification problems, define strong property-driven verification strategies, identify risk early, and improve verification quality across the broader CPU DV effort.

The primary technical scope includes formal verification of CPU core units such as frontend, midcore control logic, issue and commit behavior, load-store interactions, clock-gating and control logic, and other bounded or high-risk microarchitectural behaviors where exhaustive reasoning provides strong value.

• Own formal verification planning and execution for one or more high-performance out-of-order CPU core areas, from block-level proof strategy through signoff-oriented closure.

• Develop formal verification plans based on architectural intent and microarchitectural risk, including assumptions, assertions, covers, abstraction strategy, and closure criteria.

• Create and maintain scalable formal environments, property sets, checkers, harnesses, and proof infrastructure for complex CPU control, ordering, and interface behavior.

• Target high-value CPU verification problems such as pipeline control, issue and dispatch correctness, flush and replay behavior, register/data movement correctness, load-store ordering, hazard handling, forward progress, and clock-gating correctness.

• Use the right mix of abstraction, decomposition, bounded proofs, connectivity checks, X-prop style reasoning, and bug-hunting strategies to improve proof convergence and debug efficiency.

• Analyze proof failures, counterexamples, vacuity, over-constraint, and incompleteness, and drive fixes across RTL, properties, assumptions, and verification infrastructure.

• Partner closely with architecture, RTL, and simulation-focused DV engineers to review specifications, identify ambiguities early, and align formal results with broader verification goals.

• Contribute reusable formal methodology, automation, debug workflows, and infrastructure that improve productivity and verification quality across future CPU core programs.

• Mentor other engineers through reviews, property-quality guidance,…