PCIe Design Verification Intern: Debug, Tests & Automation
Listed on 2026-10-17
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Engineering
Test Engineer
NVIDIA in Santa Clara, CA is seeking a PCIe Design Verification Intern for a six-month term (Feb 2027–Aug 2027) to join our world‑class hardware team.
You’ll work in an SV/UVM test-bench to verify PCIe and CXL hardware functionality and performance, coding features, test plans, and automation, with global collaboration.
This internship provides hands-on hardware verification, debugging, and performance analysis with intern benefits.
The PCIe Design Verification Intern:
Debug, Tests & Automation position in the IT & Technology, Other field is open for applications.
Full responsibilities and requirements are described in the listing above.
Learn more about the PCIe Design Verification Intern:
Debug, Tests & Automation role in the description above.
We appreciate your interest in this position.
Join NVIDIA and contribute to our ongoing work.
Take a moment to read everything above and see whether this role is right for you.
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