Senior DFT & ATPG Engineer SoC/ASIC
Listed on 2026-10-17
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Engineering
Electronics Engineer, Test Engineer, Hardware Engineer
AllianceIT Inc is seeking a seasoned DFT/ATPG engineer to drive testability for complex SoC/ASIC designs in a fast-paced environment. You will apply ATPG pattern generation, analysis, and debug to ensure robust fault coverage.
The role requires strong RTL fundamentals, clock DFT knowledge, MBIST experience, and proficiency with industry-standard DFT/ATPG EDA tools, plus effective communication in high-performance programs.
This role, Senior DFT & ATPG Engineer for SoC/ASIC at AllianceIT Inc, could be your next move.
The Senior DFT & ATPG Engineer for SoC/ASIC position in the Engineering field is open for applications.
We have an opening for a Senior DFT & ATPG Engineer for SoC/ASIC in Santa Clara, CA, United States within Engineering.
This role, Senior DFT & ATPG Engineer for SoC/ASIC at AllianceIT Inc, could be your next opportunity.
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