Sr. Memory Validation Engineer

Memory is where a lot of system-level problems come to die. Marginal timing, a corner-case power state transition, a customer platform that fails one boot in ten thousand — these issues are expensive to reproduce, slow to root-cause, and they tend to come back.

We're hiring an engineer onto our ASIC design team to change that. You'll own the data and automation layer for our memory subsystem: building the test infrastructure that catches instability early, turning lab and field data into insight, and feeding what you learn back into the design of our next-generation memory controllers.

This is a role for someone who likes both the oscilloscope and the dataframe. You'll spend time in the lab on silicon bring-up and just as much time writing the automation that means nobody has to do that debug by hand next time.

• Own the memory training and calibration code. You'll develop, maintain, and tune the training and calibration routines that get LPDDR5/5X and LPDDR6 running reliably at speed across parts, boards, and operating conditions.
• Collect and analyze memory subsystem data from lab testing, customer platforms, and internal validation systems.
• Build automation for memory stability testing, performance characterization, speed binning, and regression analysis — expanding test coverage while cutting cycle time.
• Debug real customer issues alongside field teams and internal engineering groups, driving problems from first report to root cause to closure.
• Turn system behavior and failure analysis into insight that measurably improves memory controller robustness and performance.
• Influence future silicon. Propose architectural and design enhancements for next-generation memory controllers, backed by empirical data, customer feedback, and field experience.
• Validate power-saving features
  , characterizing them against performance, reliability, and power targets across a wide range of real-world use cases.
• Support silicon bring-up, qualification, and production readiness for memory subsystems.

• Beyond closing individual issues, this role exists to create durable leverage:
• Stronger memory stability and reliability across the product line
• Dramatically shorter debug and validation cycles through automation
• Faster root-cause analysis and issue closure — which customers feel directly
• A lasting repository of memory characterization data and validation best practices
• Real-world insight that shapes future memory controller designs, so recurring issues stop recurring

• 4+ years in memory validation, memory controller design, SoC validation, or a closely related area
• Hands-on experience with LPDDR5/5X and LPDDR6, and working familiarity with the relevant JEDEC specifications
• Experience owning or contributing to memory training and calibration code, with the C/firmware skills to maintain it Strong Python (or equivalent) for test automation and data analysis
• Practical debug skills on real hardware: bench instrumentation, protocol analyzers, logic analyzers, boot and stability failure triage
• Comfort with data at scale — you can take a pile of shmoo, margining, or regression results and find the signal in it
• Ability to work directly with customers and cross-functional teams under time pressure

• 1. Silicon bring-up or post-silicon validation experience on a production program
• 2. Signal integrity fundamentals: eye diagrams, jitter, and timing margin analysis on high-speed interfaces
• 3. Experience with low-power state validation (self-refresh, power-down, DVFS-style transitions)
• 4. Statistical analysis, ML, or dashboarding experience applied to hardware validation data
• 5. Firmware or driver-level exposure to the memory stack

Running memory at…