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Sr. Module Engineer, Hybrid Bonding

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: Applied Materials, Inc.
Full Time position
Listed on 2026-10-20
Job specializations:
  • Engineering
    Electrical Engineering, Process Engineer, Systems Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 147000 - 202500 USD Yearly USD 147000.00 202500.00 YEAR
Job Description & How to Apply Below
## Sr. Module Engineer, Hybrid Bonding Apply:
Santa Clara,CA:
Full time:
Posted 4 Days Ago:
R2628097
** Who We Are
** Applied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry.

The work we do together advances the world’s technology.  
** What We Offer
** Salary:$ - $

Location:

Santa Clara,CAYou’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more.

At Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits.

As a Process Engineer, you'll play a crucial role in designing and optimizing manufacturing processes for display and semiconductor manufacturing technologies. You will collect and analyze data, perform hardware characterization, and troubleshoot engineering issues. You'll also measure film properties, generate technical documentation, and engage with customers to resolve concerns. Process Engineers collaborate with vendors and suppliers, and become familiar with implementing new technologies and products.

You will experiment, learn, and collaborate with some of the brightest minds in the semiconductor and display industries, partnering with our globally recognized R&D teams on state-of-the-art research and development projects.  ## Position Summary We are seeking a highly motivated
** Die-to-Wafer Hybrid Bonding Module Engineer
** to develop and scale next-generation hybrid bonding technologies for advanced semiconductor packaging applications including Memory, chiplets, AI accelerators, photonics, and heterogeneous integration platforms.

The successful candidate will lead process module development across die preparation, surface activation, die placement, hybrid bonding, post-bond characterization, yield improvement, and manufacturing scale-up. This role requires close collaboration with equipment development teams, process integration engineers, materials scientists, device architects, and external ecosystem partners.

The position is ideal for candidates passionate about enabling future high-bandwidth and energy-efficient computing systems through advanced interconnect technologies. Hybrid bonding technologies including copper-copper and dielectric-dielectric direct bonding are critical enablers for next-generation 3D integration and HBM stacking.#

Key Responsibilities ### Hybrid Bonding Process Development
* Develop and optimize die-to-wafer (D2W) hybrid bonding processes for advanced packaging applications.
* Establish process windows for:  + Surface preparation  + Plasma activation  + Die placement  + Alignment and overlay control  + Bonding temperature and pressure optimization  + Post-bond annealing
* Drive Cu-Cu and dielectric-dielectric interconnect formation with focus on electrical performance and reliability.### Process Integration
* Support integration of hybrid bonding into:  + Memory architectures  + Chiplet-based systems  + Silicon interposers  + System-on-Wafer platforms  + Co-packaged…
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