Senior Chip Design Engineer - Tapeouts & IC Validation
Listed on 2026-10-20
-
Engineering
Systems Engineer, Electronics Engineer, Quality Engineering, Test Engineer
Applied Materials in Santa Clara, CA is seeking an experienced IC Design/Validation professional for a full-time role with up to 20% travel. The position requires deep expertise in chip design and silicon validation, along with experience in multiple tape-outs and strong cross-functional collaboration to address complex engineering challenges.
The role emphasizes proactive problem solving, technical communication, and adherence to project schedules and milestones within a global team.
We are currently recruiting a Senior Chip Design Engineer
- Tapeouts & IC Validation for our team in Santa Clara, CA, United States.
Our team is growing, and we are hiring a Senior Chip Design Engineer
- Tapeouts & IC Validation in Santa Clara, CA, United States.
This role is for the Senior Chip Design Engineer
- Tapeouts & IC Validation role at Applied Materials, Inc.
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