ASIC Design Engineer: RTL & Microarchitecture, Equity
Listed on 2026-10-20
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Engineering
Hardware Engineer, Test Engineer, Electronics Engineer, Systems Engineer
NVIDIA is seeking an ASIC Design Engineer in Santa Clara to build powerful SoC and GPU products. You will draft microarchitectures, implement RTL in Verilog, and drive verification across multiple IPs including GPU components.
The role requires 2+ years of RTL experience, strong Verilog skills, and proficiency in Perl/Python. You will collaborate with architects and verification teams to ensure high-performance, area- and power-efficient designs.
This posting is for the ASIC Design Engineer: RTL & Microarchitecture, Equity role at NVIDIA Corporation, based in Santa Clara, CA, United States.
We invite applications for the ASIC Design Engineer: RTL & Microarchitecture, Equity position located in Santa Clara, CA, United States.
The following opportunity is for a ASIC Design Engineer: RTL & Microarchitecture, Equity with NVIDIA Corporation.
Our organisation is growing, and we are hiring a ASIC Design Engineer: RTL & Microarchitecture, Equity in Santa Clara, CA, United States.
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