VLSI Design Verification Intern – AI-Enhanced IP & Silicon
Listed on 2026-10-20
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Engineering
Test Engineer
Global Foundries in Santa Clara, CA invites interns to join the Foundation IP team to support verification across standard-cell libraries, memories, and chip-level integration.
You will gain hands-on experience with circuit and logic simulation, formal verification, performance modeling, and AI-assisted methods, while developing automation scripts and CAD tooling. A 40-hour workweek and strong GPA are expected.
We are currently recruiting a VLSI Design Verification Intern – AI-Enhanced IP & Silicon for our team in Santa Clara, CA, United States.
We are seeking a motivated VLSI Design Verification Intern – AI-Enhanced IP & Silicon to join Logi Code in Santa Clara, CA, United States.
Consider building your career as a VLSI Design Verification Intern – AI-Enhanced IP & Silicon at Logi Code.
The VLSI Design Verification Intern – AI-Enhanced IP & Silicon position in the IT & Technology, Other field is open for applications.
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