PCIe Design Verification Intern: Validate AI Hardware; SV/UVM
Listed on 2026-10-21
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Engineering
Test Engineer
NVIDIA Corporation in Santa Clara, CA is seeking a PCIe Design Verification Intern for a six‑month role from February 2027 to August 2027. The position involves working in an SV/UVM test bench to verify PCIe and CXL hardware functionality and performance.
The role requires pursuing a BS or MS in CS, CE, EE or related fields with exposure to architecture/verification; familiarity with System Verilog and scripting in Python or Perl is valued.
For the PCIe Design Verification Intern:
Validate AI Hardware (SV/UVM) position at NVIDIA Corporation, we are reviewing applications now.
Full responsibilities and requirements are described in the listing above.
Learn more about the PCIe Design Verification Intern:
Validate AI Hardware (SV/UVM) role in the description above.
We appreciate your interest in this position.
Join NVIDIA Corporation and contribute to our ongoing work.
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