Senior ASIC Clocks Architect - RTL & GPU/CPU Timing
Listed on 2026-10-21
-
Engineering
Hardware Engineer, Systems Engineer, Test Engineer, Electronics Engineer
NVIDIA Corporation is seeking a Senior ASIC Design Engineer for the Clocks IP team in Santa Clara, CA. You will architect clock domains, collaborate across GPU/CPU teams, and push for performance, power, and area improvements while delivering robust clock RTL to verification and DFT groups.
You should have a BS in EE (MS preferred) and 3+ years in RTL design and verification, with strong Python skills and awareness of sub-micron silicon challenges.
We have an opening for a Senior ASIC Clocks Architect - RTL & GPU/CPU Timing in Santa Clara, CA, United States within Engineering.
Learn more about the Senior ASIC Clocks Architect - RTL & GPU/CPU Timing role in the description above.
We appreciate your interest in this position.
Join NVIDIA Corporation and contribute to our ongoing work.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).