Senior Silicon Power, Thermal Validation and Methodology Engineer

NVIDIA has been redefining computer graphics, desktop gaming, and enhanced computing capabilities for more than 25 years. Today, we are tapping into the unlimited potential of AI to define the next era of computing. As a NVIDIAN, you will work on problems that sit at the boundary of architecture, silicon, firmware, software, and production, where strong judgment matters as much as technical depth.

We're the Silicon Design for Productization (DFP) Team, within the broader Silicon Co-Design Group, and we turn power and thermal design into executable productization methodology. Power and thermal are among the most complicated problems we work on at NVIDIA because they sit at the intersection of architecture, workload behavior, silicon variation, firmware policy, platform constraints, and product goals. Small decisions here have an outsized impact on performance, efficiency, reliability, bring-up speed, and ultimately what the product can deliver in the field.

We define how features move from concepts to bring-up, characterization, validation, and release. In this role, you will help us build that bridge. We're looking for an engineer who reasons from first principles, flourishes with ownership in a fast-paced environment, and uses AI with sound judgment.

• Lead the effort across multi-functional teams to keep the program's power and thermal productization strategy clear, executable, and on track.
• Create methodology and silicon test plan based controller designs and architecture, including characterization process, debug tools, fuse/firmware settings and lab requirements.
• Drive resolution for challenging silicon issues through structured hypotheses, measurement plans, and root-cause closure.
• Steward the Power and Thermal playbook when the existing productization methodology does not fit the problem, creating new mitigations and assembling them as reusable methods.
• Build AI-enabled workflows to automate data analysis, metric extraction, trend checks, and report generation across multiple bringups to improve, leverage, and shorten time to market.
• Serve as a key technical owner for multi-functional decisions, issues, and tradeoffs related to feature bring-up.

• BS or MS in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
• 8+ years of proven track record in post-silicon bring-up and validation of power and thermal features on sophisticated ASIC or SoC programs.
• Strong end-to-end understanding of silicon behavior across architecture, firmware, validation, and platform interactions, with expertise in power and thermal domains.
• Evidence of creating/improving characterization docs, debug tools, dashboards, or other reviewable technical artifacts.
• Demonstrated ability to make sound tradeoff decisions across power, thermal, performance, firmware, design, validation, and schedule constraints.
• Shown experience building or applying AI-enabled workflows for silicon characterization or validation, with measurable workflow impact and clear validation difficulty, observability, and guardrails.

• A history of building technical power and thermal methodology, such as debug frameworks, validation standards, or characterization infrastructure.
• Experience with silicon power measurement, energy-efficiency tuning, characterization infrastructure, or analytics that improved bring-up, signoff, or validation workflows.
• Comfort working through ambiguity with globally distributed teams and a habit of surfacing the right risks, tradeoffs, and recommendations to leadership without being asked.
• Specific examples of silicon-level impact, such as faster bring-up, stronger characterization coverage, better debug turnaround, and…