Senior PCB Design Engineer
Job in
Santa Clara, Santa Clara County, California, 95052, USA
Listed on 2026-10-25
Listing for:
Arista Networks
Full Time
position Listed on 2026-10-25
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer, Hardware Engineer
Job Description & How to Apply Below
At Arista we value the diversity of thought and perspectives that each employee brings to the table. We believe that fostering an inclusive environment, where individuals from various backgrounds and experiences feel welcome, is essential for driving creativity and innovation.
Our commitment to excellence has earned us several prestigious awards, such as Best Engineering Team, Best Company for Diversity, Compensation, and Work-Life Balance. At Arista, we take pride in our track record of success and strive to maintain the highest standards of quality and performance in everything we do.
Job Description Who You’ll Work With Working closely with cross-functional teams including Hardware Design, Signal Integrity (SI), Power Integrity (PI), Mechanical Engineering, Thermal Engineering, and Manufacturing, our engineers innovate on system architectures and ultra-high-speed PCB designs to deliver state-of- the-art networking platforms.
What You'll DoOur Hardware Design Engineering team is at the forefront of developing high-speed networking and Ethernet products used in enterprise campuses, hyperscale datacenters, and next-generation AI clusters. The team is responsible for end-to-end design and development of advanced hardware solutions that meet the demands of modern networking environments — including optical interface platforms up to 800G and 1.6T.Core Responsibilities High-Speed Layout & Routing Implement complex routing for advanced interfaces such as 112G/224G Ser Des, PCIe Gen 5/6, DDR4/5/6
Design and route high-speed differential pairs with tight skew and impedance control
Execute dense BGA fan-out for high-pin-count ASICs and FPGAsOptical Transceiver PCB Layout (800G / 1.6T)
Design and layout boards supporting high-bandwidth optical transceivers (QSFP-DD, OSFP, OSFP-XD or equivalent)
Route 112G / 224G PAM4 electrical channels between switch ASICs and optical modules
Define insertion loss budgets and coordinate with SI engineers to meet IEEE compliance requirements
Optimize breakout routing beneath high-density optical cages
Implement via stub mitigation strategies including backdrilling for ultra-high-speed signal paths
Manage ground reference continuity, EMI control, and return path integrity near optical connectors
Consider thermal dissipation (20W–30W+ modules) in layout planning
Impedance Control & Signal Integrity Design advanced multi-layer stack-ups (20–30+ layers)
Calculate impedance profiles and ensure low-reflection, low-crosstalk performance
Collaborate with SI teams on channel modeling and pre-/post-layout simulations
Power Integrity (PI) Optimization Design robust Power Distribution Networks (PDNs) for high-current ASICsLayout multi-phase DC/DC converters for high transient loads
Strategically place decoupling capacitors to ensure wideband impedance stability
Thermal & Mechanical Coordination Integrate thermal vias, heat sink attachments, and high-conductivity materials
Coordinate mechanical constraints such as enclosure, airflow, and structural limitations
Ensure proper placement and structural integration of optical cages
Advanced Fabrication Deliverables Generate comprehensive manufacturing packages (Gerber, ODB++, IPC-2581)
Define…
Position Requirements
10+ Years
work experience
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