Senior Principal Design Engineer - STA​/Timing

Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AIcompute.

As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications.

Join us at Ampere and work alongside a passionate and growing team.

Ampere Computing is seeking a Senior Principal Design Engineer specializing in Static Timing Analysis (STA) and timing methodology to drive timing closure for advanced CPU and SoC designs. This highly visible technical leadership role will define timing strategies, solve complex timing challenges, and influence design, implementation, and verification methodologies across multiple projects.

The ideal candidate combines deep expertise in STA, physical design, timing analysis, and semiconductor development flows with strong leadership and communication skills. This role requires the ability to operate at both strategic and hands-on technical levels, from methodology definition through signoff and silicon readiness.

• Own and lead STA and timing-closure activities across complex CPU, SoC, and IP designs.
• Define timing constraints, analysis methodologies, signoff criteria, and implementation guidelines.
• Drive timing closure from RTL through synthesis, place and route, signoff, and tapeout.
• Analyze and resolve setup, hold, recovery, removal, pulse-width, clock-domain, and variation-related timing issues.
• Develop and maintain timing constraints, including clocks, generated clocks, false paths, multicycle paths, asynchronous paths, and interface timing.
• Lead analysis across PVT corners, RC corners, operating modes, voltage domains, and advanced variation models.
• Partner closely with RTL, microarchitecture, logic design, physical design, clocking, power, DFT, CAD, and silicon validation teams.
• Establish and improve timing methodologies, automation, dashboards, and quality checks.
• Identify timing risks early and provide architectural or implementation recommendations to mitigate them.
• Evaluate and deploy timing-analysis tools, flows, scripts, and signoff practices.
• Mentor senior and junior engineers and serve as a technical authority for STA and timing closure.
• Present timing status, risks, tradeoffs, and recommendations to engineering leadership.
• Contribute to cross-functional planning, project estimation, and execution for future CPU and SoC programs.

As a Senior Principal Engineer, you will be expected to:

• Set technical direction for STA and timing closure across programs.
• Make high-impact decisions in ambiguous and time-sensitive situations.
• Establish scalable processes and reusable methodologies.
• Raise the technical capability of the broader organization through mentoring and knowledge sharing.
• Extensive hands-on experience with STA and timing closure for complex ASIC, CPU, SoC, or high-performance digital designs.
• Strong understanding of:
  • Digital logic and synchronous design principles
  • Clock-tree design and clock-domain interactions
  • OCV, AOCV, POCV, LVF, derates, and variation-aware timing
  • Signal integrity, crosstalk, noise, and advanced-node effects
  • Multi-voltage and power-intent-aware timing analysis
  • Timing constraints and exception validation
  • MCMM analysis and signoff requirements
  • ECO implementation and timing optimization
• Experience with industry-standard tools such as Synopsys Prime Time, Prime Closure, Design Compiler, Fusion Compiler, ICC2, Cadence Tempus, Innovus, or equivalent.
• Strong scripting and automation skills using Tcl, Python, Perl, or similar languages.
• Demonstrated ability to lead complex technical efforts…