Senior Principal Design Test Engineer

Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AI compute.

As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications.

Invent the future with us.

The ideal candidate will work with multi-functional global teams to design, implement and verify Boundary Scan, ATPG (Stuck - AT/AT
- Speed) SCAN, MBIST, IO BIST and JTAG/IJTAG DFT features on our next generation highly complex server class processor products. Will work in close collaboration with test engineering team to deliver ATE patterns and post silicon bring - up and debug.

• DFT features like EDT, SSN, shared bus based MBIST insertion, ijtag , simulation and debug on RTL and gates netlist f or a uto motive app lica tion s.
• Boundary Scan insertion, simulation and verification.
• Scan insertion, Scan compression, Stuck
  - At, At
  - Speed test and coverage analysis
• Scan ATPG pattern generation, simulation and debug on RTL and gates netlist
• Hands on knowledge in state - of - the - art EDA tools for DFT, design and verification (Mentor, Cadence, Synopsys)
• STA DFT Test mode timing constraint development and analysis
• In - depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools
• ATE silicon debug and utilize scripting with perl/Tcl for efficient handling of ATE data

• Expert with methods and techniques to design, implement and verify regular and shared bus based Memory BIST on repairable and non - repairable memories using Electrical fuses.
• Expert knowledge and practical work experience partnering with designers to implement highly customized and tools - driven MBIST solutions.
• Solid understanding of MBIST algorithms needed for 5nm and lower technology nodes and ability to code new algorithms, operation sets supporting tool driven solutions for functional safety applications.
• Experience in implementing EDT, SSN , IST , boundary scan, jtag/ijtag features.
• Work independently to generate test plans, run simulations and debug failures on RTL and Gate Level.
• Hands on experience in the usage of industry standard tools, like Siemens Tessent Shell flow, or Synopsys SMS/SHS flow
• E xp erience in Mu l tim edia su bsystems DFT (Im age , displ ay , video etc. )
• Expert understanding tradeoffs to optimize coverage and test time reduction with the ability to foresee physical implementation and timing challenges during early development.
• Experience in working with physical design teams to support STA constraints, reviewing timing reports.
• Expert in using silicon debug/diagnosis tools to root cause silicon bringup and production test issue.
• Experience in setting up and running Scan DRC flows in RTL.
• Experience with industry standard simulation tools, including Verilog, and scripting languages like Perl, Python, Shell or Tcl.
• Experience in revision control systems like GIT, perforce etc.
• Needs in depth experience in stuck at, transition delay, path delay, etc. coverage loss analysis and identifying solutions to improve test coverage
• Experience in leading the effort to derive cell aware fault models and develop necessary flows to generate ATPG and to support silicon debug.
• Good knowledge of functional safety, clock domain crossing analysis, logic synthesis and scan insertion
• Electrical or Computer Engineering
  - Bachelor’s degree & 12 years of related experience; or Master's degree & 8 years; or PhD & 5 years

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