Distinguished Circuit Engineer

Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AIcompute.

As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications.

Join us at Ampere and work alongside a passionate and growing team-we’dlove to have you apply!

We are seeking a Distinguished Circuit Engineer to lead Ampere’s High-Speed I/O (HSIO) and Ser Des technical direction. This role balances two core responsibilities: leading custom in-house IP development and driving technical engagements with third-party IP vendors and foundries.

In this position, you will own the technical roadmap for our high-speed interfaces—including Die-to-Die (D2D), memory, and standard peripheral IOs—on advanced process nodes (3nm, 2nm, and beyond). Working closely with system architects, package design, and validation teams, you will have end-to-end technical responsibility from initial specification through implementation, integration, post-silicon characterization, and high-volume productization.

• In-House IP Development:
  Architect, specify, and guide the design and execution of proprietary, high-efficiency custom Ser Des and D2D PHY macros tailored to Ampere’s system requirements.
• Third-Party IP Partnership:
  Serve as the primary technical interface with external IP vendors (e.g., PHY providers) and foundries; evaluate vendor offerings, drive custom spec modifications, conduct risk assessments, and lead make-vs-buy decisions.
• End-to-End Spec Definition & Integration:
  Define detailed IP electrical, functional, and timing specifications in close collaboration with SoC architects, package design, SI/PI, and logic/DV teams to ensure clean integration into server SoCs.
• Circuit Architecture & Design Execution:
  Guide critical analog and mixed-signal circuit architectures—including TX/RX front-ends, clock generation/distribution (PLLs, reference clocks), equalization (DFE/CTLE), and calibration engines across advanced geometries.
• Post-Silicon Characterization & Debug:
  Define post-silicon validation, characterization, and lab test methodologies for both in-house and third-party IPs. Lead bring-up, BER analysis, eye-centering, and root-cause debugging for complex silicon/interconnect issues.
• Production Quality & Screening:
  Partner with product and test engineering (PE/TE) to establish HTOL, PVT validation, and production screening flows to ensure robust yield and reliability in volume manufacturing.
• System & Package Co-Design:
  Collaborate with packaging (advanced substrates, EMIB/interposers) and SI/PI teams to establish channel operating margins, crosstalk limits, and PDN specifications.
• Technical Mentorship & Influence:
  Mentor circuit and mixed-signal engineers, establish solid design methodologies, and align technical roadmaps with leadership and cross-functional teams.

• Significant experience in a Principal, Fellow, or Distinguished technical leadership capacity focusing on high-speed Ser Des / mixed-signal PHY silicon development.
• Proven Silicon Track Record:
  Extensive history of successfully taking complex, high-speed Ser Des (PAM4/NRZ, D2D, PCIe, DDR, or UCIe) from concept to high-volume production in advanced FinFET/GAA process nodes.
• Deep Mixed-Signal Expertise:
  Master of analog and mixed-signal design concepts (TX/RX front-ends, PLL/clock generation and distribution, equalizers/DFE, CDR, ADC/DAC-based Ser Des) and underlying device physics across PVT corners.
• Signal & Power Integrity Acumen:
  Strong command of high-frequency transmission line theory,…