Custom Circuit Design; Sr​/Principal

Position: Custom Circuit Design (Sr. Staff / Principal)
Bangalore / Santa Clara, CASilicon – Custom Design /Full-time /On-site

Role Overview As a Sr. Staff/Principal Custom Circuit Design Engineer at Velaura AI, you will lead the architecture, design, and optimization of high-performance, low-power standard cell libraries and custom digital circuits for next-generation AI and high-performance computing silicon. You will drive transistor-level innovation across advanced process technologies, collaborating closely with layout, characterization, physical design, CAD, and product engineering teams to deliver world-class PPA, robustness, and manufacturability.

This is a highly visible technical leadership role where you will influence library architecture, design methodologies, and next-generation circuit solutions while mentoring engineers and shaping the future of our silicon platform.

Responsibilities Lead the architecture, design, and optimization of high-performance, low-power standard cells targeting advanced process technologies with a strong focus on Performance, Power, and Area (PPA). Design and optimize transistor-level circuits including latches, flip-flops, multiplexers, AOI/OAI, XOR/XNOR, encoders, decoders, level shifters, arithmetic cells, and other complex sequential and combinational logic. Architect and develop advanced arithmetic building blocks, including adders, multipliers, integer and floating-point MAC units, for high-performance compute applications.

Develop schematics using Cadence Virtuoso and perform post-layout validation through parasitic extraction using StarRC or Quantus. Perform circuit verification across all PVT corners using HSPICE, Prime Sim XA, or Spectre, ensuring robust functionality, timing, and power performance. Drive statistical verification using Monte Carlo methodologies and advanced variation analysis with Solido, Spectre FMC, or equivalent tools. Own reliability sign-off activities, including electromigration (EM), IR-drop, self-heating, BTI/HCI aging analysis, while ensuring ESD and latch-up robustness.

Drive low-power circuit innovations through multi-Vt optimization, leakage reduction, power gating, retention strategies, isolation cells, and power-intent-aware design methodologies. Collaborate closely with custom layout teams to optimize layouts for Layout Dependent Effects (LDE), manufacturability, coloring compliance, matching, and pin accessibility. Partner with Characterization, Physical Design, STA, CAD, and Product Engineering teams to ensure successful library development, silicon readiness, and production-quality deliverables.

Drive design methodology improvements, automation initiatives, and technical best practices across the circuit design organization. Mentor engineers and provide technical leadership in circuit design, methodology development, and advanced technology enablement.

Required Qualifications 10+ years of experience in custom digital circuit design, standard cell development, or memory circuit design. Strong expertise in transistor-level CMOS circuit design for advanced technology nodes. Proven experience designing and optimizing high-performance, low-power standard cell libraries. Deep understanding of advanced process technologies including FinFET and Gate-All-Around (GAA). Extensive experience with circuit simulation tools such as HSPICE, Prime Sim XA, or Spectre.

Experience with parasitic extraction using StarRC or Quantus. Strong knowledge of statistical verification, Monte Carlo analysis, and variation-aware circuit design. Experience performing reliability verification including EM, IR-drop, aging, self-heating, and silicon robustness analysis. Demonstrated ability to drive complex technical projects from concept throughsilicon.

Preferred Qualifications Master's or Ph.D. in Electrical Engineering, Electronics Engineering, or a related discipline. Strong understanding of digital circuit architecture, standard cell design, and advanced flip-flop architectures.

Experience with standard cell characterization using Liberate or Prime Lib, including Liberty (.lib) generation and validation. Good understanding of Static Timing Analysis (STA), Liberty timing models, and ASIC sign-off methodologies. Familiarity with complete ASIC development flows from circuit design through physical implementation and silicon validation. Experience developing automation using Python, Tcl, or Perl. Track record of leading technical initiatives and mentoring engineering teams.

Experience with SRAM peripheral circuit design.…