Design Verification Engineer, Infinity Fabric and Chiplet Interconnect

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture.

We push the limits of innovation to solve the world’s most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

The Infinity Fabric transport layer verification team is looking for a Design Verification Engineer to help verify the advanced interconnect technology at the heart of AMD’s products.

In this role, you will work on configurable switches, transport-layer features, and die-to-die connectivity used across Client, Server, Graphics, and Semi-Custom products. You will collaborate with architecture, RTL design, firmware, and verification teams to solve complex technical challenges, strengthen verification methodologies, and help deliver high-quality silicon across AMD’s product portfolio.

You are passionate about processor architecture, digital design, and verification. You enjoy solving challenging technical problems, debugging complex behavior, and learning how interconnected systems work.

You are a collaborative team member with strong analytical, problem-solving, and communication skills. You work effectively with engineers across disciplines, locations, and time zones, and you are comfortable taking ownership of problems and driving them through resolution.

• Define and execute verification strategies for complex Infinity Fabric features and subsystems with cross-project and cross-product impact
• Partner with architects, RTL designers, firmware engineers, and verification teams to influence feature definition, implementation, and verification readiness throughout the design cycle
• Own verification planning and execution for technically critical areas, including identifying risks, evaluating trade-offs, and developing mitigation strategies
• Develop robust, scalable verification environments and methodologies, including directed and constrained-random testing using System Verilog and UVM
• Debug complex interactions across test benches, RTL, firmware, and architectural models and drive issues through resolution
• Solve complex and ambiguous verification challenges by developing new approaches or extending existing methodologies, processes, and infrastructure
• Analyze functional and code coverage and drive coverage closure strategies that balance quality, schedule, and compute efficiency
• Drive improvements to verification processes, tools, automation, and workflows that increase productivity, quality, and execution efficiency
• Collaborate across teams and programs to align verification activities, technical dependencies, and shared objectives
• Share technical knowledge, contribute to verification best practices, and support the technical development of the broader engineering team

• Proficiency in IP-level ASIC verification
• Experience debugging firmware and RTL using simulation and debugging tools
• Hands-on experience with UVM concepts, test benches, and System Verilog
• Experience developing UVM-based verification frameworks, test benches, processes, and flows
• Experience with Verilog, System Verilog, C, and C++
• Experience developing directed and constrained-random verification environments
• Experience with functional and code coverage analysis and coverage closure
• Experience…