Principal Foundry Interface Engineer

Requisition  Si Time Si Time  is the Precision Timing company.

Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.Our

semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: .

Job Summary In this role, the candidate will support Foundry technical interface for SiTime. The key responsibilities include the following.

It is not necessary to meet all job requirements to be a qualified candidate for the position. Responsibilities:

Lead Foundry yield improvement through mitigation of systematic and parametric yield detractors

Manage Foundry yield excursion and implementation of Continuous Improvement Plan.

Manage Foundry safe launch

Provide technical guidance on Foundry Fab transfer projects

During development, direct wafer lot progress, process skew splits and DOE strategies

Support device performance analysis for mixed signal devices.

Manage compliance with fab yield, E-test, WAT, inline Cp/CpK metrics

Experience with AI/ML predictive modeling to improve projection accuracy for test chips and high-volume products, including correlation of inline process metrics with end-of-line yield and performance, is a plus.

Serve as technical liaison to the Foundries, communicate status of process health monitors to internal stakeholders, drive on time wafer out from the fab, continuous improvement deliverables and resolution of critical technical escalations.

Qualifications & Requirements:

Minimum requirements are a Master’s degree with 13+ years of experience or a PhD with 10+ years of industry experience in a relevant engineering or physical-science field, including Semiconductor Process Integration, Device Engineering, or Wafer Yield Engineering.

English proficiency is required, including the ability to effectively communicate, collaborate, and perform job responsibilities in a professional business environment.

Proven track record in yield pareto construction, modeling, projection, and the development of long-term yield roadmaps.

Experience in using PDF Exensio or other Big Data Analysis tools.

Extensive experience collaborating with foundries.

Experience in porting between fabs.

Expertise in interpreting complex product data (inline, e-test, and SORT) to drive organization-wide solutions.

Deep knowledge of semiconductor wafer inline inspection methods and SORT programs.

Deep knowledge of semiconductor device reliability

Well versed with DFM techniques and PFMEAKnowledge and experience in RF semiconductor device modeling experience is a plus Ability to communicate in Mandarin is a plus Experience in supporting semiconductor wafer fulfillment for products that require to meet Automotive , ISO 26262 standards.

Strong Leadership and ability to set standards and drive to targets.

This position requires clear, accurate and timely communication both written and verbally.

Strong attention to detail, project management and organization skills, and ability to manage multiple projects at the same time in a fast-paced environment with minimal supervision.

Desired Characteristics & Attributes:

Strong team worker within multi-disciplinary and multi-cultural…