Sr. PCIE Subsystem Architect

Qualcomm Technologies, Inc.

Engineering Group, Engineering Group >
SoC Architecture

Job Overview:

Qualcomm is looking for an experienced PCIe Subsystem Architect to help define and deliver high-performance I/O architectures for next-generation AI products in the datacenter.

The ideal candidate is a high-speed interfaces architect with deep expertise across PCIe, CXL. The selected candidate will define subsystem architecture and drive requirements from the accelerator card and server level through full-rack scale-up and scale-out deployments.

• In-depth knowledge of PCIe, Ethernet, and other high-speed I/O interfaces used in datacenter and accelerator products.
• Strong understanding of PCIe ordering models, producer-consumer ordering, ARM ordering behavior, DMA flows, and high-speed serial interface behavior.
• Strong understanding of PCIe Gen6/Gen7 requirements, including FLIT mode, PAM4 signaling implications, link training, latency, error handling, and system-level tradeoffs.
• Experience with PCIe error containment and recovery mechanisms such as Advanced Error Reporting (AER), Downstream Port Containment (DPC), Configuration Request Retry Status (CRS), Function Level Reset (FLR), and reset separation.
• Experience with I/O virtualization and isolation technologies such as SR-IOV, SIOV, PF/VF isolation, and related software-visible requirements.
• Strong understanding of RAS, telemetry, reliability, and security requirements for server-class SoCs and accelerator subsystems.
• Good knowledge of PCIe switch fabrics, NIC connectivity, host-to-accelerator orchestration, and rack-level deployment considerations.
• Ability to work effectively in a high-caliber, international, multi-site engineering team.

• Good understanding of PCIe integrity, security, and confidential-compute features such as IDE, DOE/SPDM, TDISP, SR-IOV, and SIOV.
• Strong familiarity with PCIe CEM standards, add-in card deployment constraints, retimers, signal-integrity considerations, and system-level validation flows.
• Good understanding of emerging AI interconnect standards and ecosystems such as UCIe, UALink/UAL, and UEC.
• Good understanding of PCIe firmware, BIOS/UEFI, operating-system, driver, and system-software requirements.
• Good understanding of high-speed Ser Des and PHY technologies, including PCIe PHY, Ethernet PHY, PAM4 signaling, and power/performance tradeoffs.
• Good knowledge of server SoC architectures with emphasis on security, RAS, virtualization, IOMMU/SMMU, DMA, address translation, and telemetry.
• Ability to engage with customers, product management, systems teams, and cross-functional architecture stakeholders to gather requirements and drive technical alignment.
• Excellent written and verbal communication skills, with the ability to create architecture specifications, requirement documents, and executive-level technical summaries.

• Bachelor's degree in Electrical Engineering, Computer Science, or related field and 8+ years of Systems Engineering or related work experience.
• OR
• Master's degree in Electrical Engineering, Computer Science, or related field and 7+ years of Systems Engineering or related work experience.
• OR
• PhD in Electrical Engineering, Computer Science, or related field and 6+ years of Systems Engineering or related work experience.
• 2+ years of experience in one or more system architecture technology areas and products (e.g., Power System, Shared Resource Management, Limits/Thermal Management, Hardware Islands).

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