Advanced Packaging Technology & Integration Leader

Who We Are Applied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry.

The work we do together advances the world’s technology.

What We Offer Salary: $ - $

Location:

Santa Clara,CA You’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible while learning every day in a supportive leading global company. Visit our Careers website to learn more. At Applied Materials, we care about the health and wellbeing of our employees.

We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits.

Position Summary We are seeking an exceptional Advanced Packaging Technology & Integration Leader to lead the development of next-generation semiconductor packaging and 3D integration technologies. This individual will combine deep technical expertise, first-principles problem solving, semiconductor process integration, and technical leadership. The successful candidate will have a demonstrated history of developing new technologies by understanding the fundamental physics, materials, interfaces, processes, and integration constraints rather than simply optimizing established process flows.

The role requires broad expertise across hybrid bonding, through-silicon vias (TSVs), advanced thermal materials and thermal management, interposers, bridge-die technologies, and heterogeneous integration. The individual will lead cross-functional teams spanning materials, unit-process development, integration, device/package architecture, modeling, characterization, equipment, and manufacturing.

Develop differentiated semiconductor packaging technologies from first principles, translating fundamental understanding of materials, interfaces, mechanics, thermals, electrical performance, and process physics into practical technology solutions. Identify critical technology limitations in future AI/HPC, memory, and heterogeneous-integration architectures and develop new approaches to overcome them. Convert early concepts into experimentally testable structures, integration flows, and technology demonstrations. Establish technology roadmaps connecting future device and package requirements to new materials, processes, equipment capabilities, and integration schemes.

Evaluate competing technical approaches and make clear recommendations based on fundamental engineering trade-offs.

Provide technical leadership across areas including:
Wafer-to-wafer and die-to-wafer hybrid bonding, Cu-Cu and dielectric bonding interfaces;
Bond-pad scaling, planarity, surface preparation, overlay, and alignment; TSV formation and integration, including via etch, liner/barrier/seed, fill, reveal, stress, and wafer-thickness considerations; 2.5D and 3D integration;
Silicon and alternative interposers;
Bridge-die architectures and integration;
Chiplets and heterogeneous integration;
Advanced redistribution and high-density interconnects;
Thermal materials and thermal-management integration;
Backside and embedded thermal-management concepts;
Warpage, stress,…