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Server Structural FEA Engineer

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: Qualcomm
Full Time position
Listed on 2026-11-02
Job specializations:
  • Engineering
    Systems Engineer, Mechanical Engineer, Test Engineer, Materials Engineering
Salary/Wage Range or Industry Benchmark: 190200 - 285400 USD Yearly USD 190200.00 285400.00 YEAR
Job Description & How to Apply Below
Company

Qualcomm Technologies, Inc.

Job Area

Engineering Group, Engineering Group >
Systems Engineering

General Summary

Qualcomm's Data Center team is developing high-performance, energy-efficient server solutions for data center applications. We are looking for highly talented, innovative, and collaborative individuals to contribute to cutting-edge server technology development.

Our Mission

We are dedicated to transforming the industry by reimagining silicon and developing next-generation computing platforms. By joining our team, you will collaborate with world-class engineers to create innovative solutions that advance performance, energy efficiency, scalability, and reliability. Our focus is on developing reference platforms based on Qualcomm Snapdragon SoCs and delivering comprehensive hardware and software solutions, reference designs, user guides, SDKs, and related enablement.

Position

Summary

We are seeking a Staff / Senior Staff Server Structural FEA Engineer with deep expertise in semiconductor package mechanics, structural reliability, and advanced finite element analysis. The role focuses on structural integrity and reliability of server SoCs, spanning die- and package-level behavior through interaction with the server platform. The scope includes both soldered and socketed SoC packages and their mechanical interaction with PCBs, sockets and retention systems, cooling solutions, and thermal interface materials, including TIM
1.5.

Key Responsibilities
  • Develop and apply advanced structural and thermo-mechanical FEA methodologies for server SoCs and advanced semiconductor packages, including CPI, package assembly, warpage, stress, deformation, and structural reliability.
  • Evaluate both soldered and socketed packages under package assembly, SMT, socket and retention loading, cooling-system loading, temperature cycling, qualification, and operating conditions.
  • Analyze package-to-platform mechanical interaction among the SoC package, PCB, socket or retention system, heatsink or cold plate, and thermal interface materials, including TIM
    1.5.
  • Apply advanced FEA techniques including submodeling, contact analysis, material and geometric nonlinearity, viscoelasticity, creep, fatigue, fracture or damage mechanics, and coupled structural-thermal analysis as appropriate.
  • Develop physics-based reliability and life-prediction models for relevant failure mechanisms, including solder and bump fatigue, die and BEOL stress, substrate and interposer cracking, delamination, and creep. Perform BLR and solder-joint reliability analyses to quantify damage accumulation, design margins, and expected life.
  • Perform sensitivity, uncertainty, and bounding analyses to identify dominant parameters, quantify structural risk, and guide package and platform architecture decisions before hardware is available.
  • Define model-validation and correlation strategies using material characterization, package/board measurements, reliability and qualification testing, manufacturing data, and system-level test results, including development of test vehicles and methods where needed.
  • Partner with package engineering and computational modeling teams to align modeling assumptions, material properties, process inputs, boundary conditions, revision control, correlation methodologies, and failure criteria.
  • Develop independent analyses, sensitivity studies, or targeted model cross-checks as needed to reconcile differing predictions, quantify uncertainty, and evaluate server-specific package-to-platform boundary conditions.
  • Work closely with system/platform structural-analysis engineers to provide package mechanical properties, load limits, deformation behavior, and failure criteria supporting broader platform, system, and rack-level lifecycle analyses.
  • Apply expertise in package architectures and substrate technologies, including FCBGA, FCLGA/HFCBGA, chiplet-based designs, HBM integration, 2.5D interposers or bridges, and 3D packaging technologies.
  • Develop scalable workflows, automation, modeling standards, best-known methods (BKMs), and validation frameworks. Experience with ANSYS APDL-based workflow development is strongly preferred.
  • Translate complex simulation results into clear design requirements and recommendations for cross-functional engineering teams, leadership, customers, and suppliers.
Qualifications
  • Master's degree in Mechanical Engineering, Engineering Mechanics, Materials Science, Physics, or a related field.
  • 10+ years of advanced FEA experience in semiconductor…
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