Senior ASIC PD Engineer - Cache Coherent Interconnects

NVIDIA Corporation in Santa Clara, CA seeks a CPU Cache Coherent Interconnects Design Engineer to own the physical design of the on-chip interconnect network and last-level caches. You will perform synthesis, timing closure, and power optimization while collaborating with the logic team on micro-architecture feasibility.

You will evaluate PD for next-generation Nvidia coherent interconnects and system-level caches, contribute to RTL design/verification, and navigate the ASIC flow with DFT/ECO

The following opening is for a Senior ASIC PD Engineer
- Cache Coherent Interconnects with NVIDIA Corporation.

The Senior ASIC PD Engineer
- Cache Coherent Interconnects position in the Engineering field is open for applications.

We have an opening for a Senior ASIC PD Engineer
- Cache Coherent Interconnects in Santa Clara, CA, United States within Engineering.

This role, Senior ASIC PD Engineer
- Cache Coherent Interconnects at NVIDIA Corporation, could be your next move.