Senior GPU Physical Design Engineer

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings.

We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.

As a GPU Physical Design Engineer, you will play a critical role in the physical implementation of cutting-edge GPU designs from RTL to GDS, ensuring optimal performance, power, and area. You will be responsible for executing key aspects of the physical design flow, including synthesis, place and route, timing analysis, and verification, driving the success of Intel's next-generation graphics products.

You will join Intel's Data Center Group (DCG), a team dedicated to creating innovative technologies for data center and enterprise solutions. DCG focuses on delivering high-performance computing systems, enabling Intel's mission to advance data-driven insights and empower businesses worldwide.

• Perform physical design implementation of GPU designs, including synthesis, placement, routing, and clock tree synthesis.
• Conduct verification and signoff tasks, such as static timing analysis, layout verification, and formal equivalence checking.
• Analyze results and collaborate with cross-functional teams to optimize design for power, frequency, and area.
• Develop and improve physical design methodologies and flow automation for continuous innovation in GPU physical design.
• Address GPU development challenges by defining product requirements and implementing tailored methodologies for advanced process nodes.

Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.

Minimum qualifications are required to be initially considered for this position.

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 6+ years of relevant experience, or Master's degree with 4+ years of experience, or PhD with 2+ years of experience.
• Experience with ASIC design flows such as floor planning, synthesis, place and route, and layout verification.
• Advanced experience in industry-standard tools such as Fusion Compiler, Genus/Innovus, ICC-DP, Prime Time, StarRC, and Formality.
• Advanced scripting skills in Tcl, Python, or similar languages for flow automation and optimization.

Minimum qualifications are required to be initially considered for this position.

• Experience with GPU physical design challenges, including SoC integration and timing closure.
• Background in optimizing power, performance, and area for designs on advanced process nodes.
• Familiarity with Unix/Linux-based environments and methodologies for tool and flow development.

Experienced Hire

Shift 1 (United States of America)

US, California, Folsom

US, California, Santa Clara, US, Oregon, Hillsboro

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $ -  USD

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
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