Principal Physical Design Engineer

Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.

Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit:  .

SiTime is seeking a seasoned Principal Physical Design Engineer to lead the physical implementation and signoff of complex digital blocks and subsystems. The successful candidate will take end-to-end ownership from synthesis and floor planning through GDSII signoff, driving power, performance, area, reliability, and schedule outcomes.

This role serves as a technical leader for physical design, shaping implementation methodology and automation, resolving complex cross-functional challenges, and establishing engineering best practices across multiple programs.

We value diverse experiences, perspectives, and career paths, and welcome candidates who are excited to contribute to our mission.

• Serve as the technical focal point for physical design, leading implementation and signoff reviews, mentoring engineers, and establishing reusable methodologies across multiple programs.
• Lead and execute end-to-end physical design for complex digital blocks and subsystems, from synthesis through GDSII signoff, including floor planning, power planning, place and route, clock tree synthesis, static timing analysis (STA), formal equivalence check, design rule checking (DRC), layout versus schematic (LVS), power, and EMIR.
• Develop and continuously improve automated, reproducible physical-design and signoff flows to increase productivity, reduce execution risk, and ensure consistent design quality across multiple programs.
• Participate actively in architecture and design-specification reviews, providing physical-implementation insight early to avoid downstream PPA, signoff, and schedule risks.
• Architect and apply low-power implementation strategies including clock gating, power gating, power‑aware implementation and multi‑voltage design to meet product‑level power budgets.
• Work closely with the chip‑top layout and integration teams to integrate digital blocks into mixed‑signal, custom‑layout top‑level designs, resolving physical, DRC, LVS, power, clock, EMIR, and connectivity issues at block boundaries.

It is not necessary to meet all job requirements to be a qualified candidate for the position.

• BS. in Electrical Engineering, Computer Engineering, or a related field with a minimum of 10 years of relevant experience, or a Ph.D. with a minimum of 6 years of relevant experience.
• Hands‑on ASIC physical design experience, with a clear record of driving designs from concept through successful tape‑out on advanced process nodes.
• Deep hands‑on experience with industry‑standard physical implementation and signoff tools, such as Cadence Innovus or Synopsys IC Compiler II/Fusion Compiler, together with STA, formal, physical‑verification, and power‑integrity platforms.
• Strong scripting capability in Tcl, Perl, and/or Python, applied to flow automation, constraint generation, and custom reporting.
• Strong understanding of SDC timing constraints and concurrent MMMC optimization throughout the…