Power-Aware CPU RTL Design Engineer
Listed on 2026-11-05
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Engineering
Hardware Engineer, Electronics Engineer, Test Engineer, Electrical Engineering
Qualcomm Technologies, Inc. in Santa Clara, CA is seeking a Low Power RTL Design Engineer to contribute to power-aware CPU RTL development. You will work with chip architects to specify power architecture and drive UPF-based power intent across RTL to physical implementation.
The role emphasizes experience with Verilog/System Verilog, UPF, and Conformal Low Power, along with timing and power considerations. Collaboration with cross-functional teams is essential.
This opportunity is for the Power-Aware CPU RTL Design Engineer role at QUALCOMM, Inc.
The position is based in Santa Clara, CA, United States.
This opportunity is part of our work in Engineering.
The advertised compensation is 124..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Power-Aware CPU RTL Design Engineer role in the description above.
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