Front-End CPU Verification Engineer - Unit-Level DV

Tenstorrent is seeking a Design Verification Engineer to contribute to unit‑level verification of the RISC‑V CPU front end, including instruction fetch, branch prediction, and related fetch control structures. The role emphasizes building test benches, generating stimulus, and developing checkers in System Verilog, UVM, and C++.

This hybrid role is based in Austin, TX or Santa Clara, CA, with candidacy for various experience levels. Offers align with the level during interviews.

For the Front-End CPU Verification Engineer
- Unit-Level DV position at Tenstorrent, we are reviewing applications now.

We are seeking a motivated Front-End CPU Verification Engineer
- Unit-Level DV to join Tenstorrent in Santa Clara, CA, United States.

Consider building your career as a Front-End CPU Verification Engineer
- Unit-Level DV at Tenstorrent.

The Front-End CPU Verification Engineer
- Unit-Level DV position in the IT & Technology, Engineering field is open for applications.