Principal Device and Compact Modeling Engineer; 2D TMD Tiers

Measure our first all-MoS₂ memory cell hot and build the models we design on

Phanta Field designs chips built by growing memory and logic tiers of 2D semiconductors such as MoS₂, a few atoms thick, on top of finished silicon wafers at low temperature. Van der Waals is our 3D DRAM family, and Side S64 goes first: a memory die that sits beside the GPU, where HBM sits today. Sophon is our AI chip: one 750 mm² die with 64 tiers grown over 28 nm logic, holding 330 GB of DRAM inside the compute array.

MoS₂ transistors have been measured, and so has a capacitor-less 2T0C memory cell with a MoS₂ write transistor that holds data past 1,000 seconds. Van der Waals and Sophon are designs: every chip-level figure here is modeled from those measurements. Prof. Chenming Hu, co-inventor of the FinFET, was our first investor and advises us.

Every memory number we have depends on a cell we have not measured yet. The 2T0C cell measured so far uses a MoS₂ write transistor over a silicon read transistor, and no tier can use a silicon transistor. You will specify and measure the first all-MoS₂ cell, hot, on tiers grown in runs we buy at outside sites until we have our own lab.

Then you turn that data and the transistor data into the compact models our tier PDK and our Sophon models are built on. You report to the CEO and lead the device, characterization and PDK team.

HOT CELL Specify and measure our first all-MoS₂ 2T0C cell at 25, 85, 95 and 105 °C on a rail of 1 V or less. Report the weak-bit tail, the row cycle and the write pulse along with the typical cell.

LEAKAGE Measure tier-select off-current at 105 °C against a budget of about 210 pA per gate, and the read margin that follows from it.

COMPACT MODELS Extract compact models with corners and temperature. Model write-wordline kickback and coupling between read wordlines and read bitlines. These models become the device layer of our tier PDK and calibrate our Sophon models.

CELL LAYOUT Check the 8F² cell layout against the retention you measure.

DATA OWNERSHIP Get data ownership agreed in writing before any outside-lab measurement goes into the PDK.

• Education:
  
  PhD, plus 8+ years in FET device physics. 2D or oxide-semiconductor channels preferred.
• Leakage:
  You have measured pA-level leakage and retention on a hot chuck.
• Models:
  You have extracted compact models in Verilog-A or BSIM style, with corners and temperature.
• TCAD:
  You use TCAD to explain what you measure.
• Statistics:
  You report distributions and their tails.
• Outside labs:
  You can plan and run measurements at labs you do not own.

• Gain-cell or eDRAM device work.
• Statistical variability modeling.
• Contacts and gate stacks on MoS₂ or other 2D channels.

You define the cell everything else is designed around. The test conditions are already written down, from 25 to 105 °C on a rail of 1 V or less, so the job is measurement and modeling with clear pass marks. Your models become the device layer of the PDK for two products.

Phanta Field is an equal opportunity employer. We consider all qualified applicants without regard to race, color, ancestry, national origin, religion, creed, age (40 and over), physical or mental disability, sex, gender (including pregnancy, childbirth, breastfeeding and related conditions), sexual orientation, gender identity, gender expression, medical condition, genetic information, marital status, military or veteran status, reproductive health decision-making, or any other basis protected by law.

This role involves technology subject to U.S. export controls. Employment may depend on obtaining any required U.S. government authorization.