Power‑Management CPU Architect & RTL Design Engineer
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Engineering
Job Description & How to Apply Below
SiFive, Inc. seeks a Power‑Management/Reset/Clock Micro‑Architect and RTL Design Engineer in Santa Clara to design leading CPU and interconnect IP. You will collaborate with various teams to define specifications and optimize power-management features, ensuring high-quality design and performance.
The ideal candidate will have a BS/MS in EE, CE, or CS, and be proficient in RTL design with 3+ years experience in CPU or SoC design. The role offers a salary range of $158,760 – $194,040 and comprehensive benefits.
We have an opening for a Power‑Management CPU Architect & RTL Design Engineer in Santa Clara, CA, United States within Engineering.
The advertised compensation is 158..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Power‑Management CPU Architect & RTL Design Engineer role in the description above.
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