Senior ASIC Timing Engineer DFT/STA & ECOs
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Engineering
Job Description & How to Apply Below
NVIDIA in Santa Clara, CA seeks a timing engineer to drive STA for DFT logic across GPUs/SoCs. You will collaborate with PD, DFX and Clocks teams to define constraints, ensure timing closure, and implement ECOs, while increasing automation and standardization.
Required:
BS or MS in Electrical/Computer Engineering with 2+ years (MS) or 5+ years (BS) of STA experience, strong hands-on with timing paths, ECOs, and timing tools. Equity and a strong benefits package accompany this role.
Join us at NVIDIA Corporation as our next Senior ASIC Timing Engineer for DFT/STA & ECOs in Santa Clara, CA, United States.
Please review the full job details above before applying.
If your experience matches this role, we encourage you to apply.
All applications are reviewed carefully by our team.
The position is based in Santa Clara, CA, United States.
Position Requirements
10+ Years work experience(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
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