Formal Verification Engineer — Build -Gen Silicon; Equity
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Engineering
Job Description & How to Apply Below
NVIDIA in Santa Clara, CA is seeking a Formal Verification Engineer to join our team responsible for verifying RTL units of next generation chips. You will own the verification plan, build test environments, and apply advanced formal techniques to ensure correctness and reliability.
The ideal candidate has a CS/CE/EE/Math degree, strong analytical ability, experience with Verilog/System Verilog and formal tools (Jasper, IFV, SMV, SPIN), and excellent communication to collaborate with design
We are seeking a motivated Formal Verification Engineer — Build Next-Gen Silicon (Equity) to join NVIDIA in Santa Clara, CA, United States.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Formal Verification Engineer — Build Next-Gen Silicon (Equity) role in the description above.
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