Hands-On Memory Subsystem Verification Engineer

Qualcomm Technologies, Inc. is seeking a Design Verification Engineer to drive memory subsystem verification, including memory controllers, DDR/LPDDR/HBM interfaces, and PHY logic.

You will develop and execute verification strategies, build UVM-based test benches, and write assertions, covering multiple modes and addressing complex verification challenges. The role requires strong Verilog/System Verilog/UVM skills, experience with constrained-random verification, and collaboration with RTL,

The Hands-On Memory Subsystem Verification Engineer position in the IT & Technology, Engineering field is open for applications.

We aim to respond to suitable candidates as soon as possible.

Full responsibilities and requirements are described in the listing above.

Learn more about the Hands-On Memory Subsystem Verification Engineer role in the description above.

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