Senior Verification Engineer: SystemVerilog/UVM SoC
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Engineering
Job Description & How to Apply Below
iFlow Inc. is seeking a Design Verification Engineer based in Santa Clara, CA, for a long-term position. The successful candidate will possess 8-15 years of experience, showcasing a strong proficiency in System Verilog and UVM, alongside debugging skills.
Key responsibilities include developing verification environments for testing, performing coverage analysis, and collaborating with RTL designers to debug simulation failures while ensuring design quality across various domains.
This role is for the Senior Verification Engineer:
System Verilog/UVM for SoC role at iFlow Inc.
Step into the Senior Verification Engineer:
System Verilog/UVM for SoC role at iFlow Inc. in Santa Clara, CA, United States and grow with us.
Please review the full job details above before applying.
If your experience matches this role, we encourage you to apply.
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Position Requirements
10+ Years work experience(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
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