VLSI Physical Design Intern: Floorplanning to Timing
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Engineering
Job Description & How to Apply Below
NVIDIA Corporation in Santa Clara, CA offers a 12-week, full-time Hardware Physical Design / VLSI internship where you will work on projects with measurable impact across floor planning, placement, timing analysis, and power integrity. You should be enrolled in a B.S., M.S., or Ph.D.
program in Electrical/Computer Engineering or a related field, with experience or coursework in VLSI, CAD tools, and scripting.
Our team is growing, and we are hiring a VLSI Physical Design Intern:
Floor planning to Timing in Santa Clara, CA, United States.
We have an opening for a VLSI Physical Design Intern:
Floor planning to Timing in Santa Clara, CA, United States within Engineering, Other.
This role, VLSI Physical Design Intern:
Floor planning to Timing at NVIDIA Corporation, could be your next career step.
Are you ready to take on the VLSI Physical Design Intern:
Floor planning to Timing role at NVIDIA Corporation?
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