Senior Timing Architect - 5nm Custom Circuits & Equity

A leading technology company in Santa Clara is seeking an innovative Senior Timing Methodology Engineer to develop timing sign-off strategies for advanced GPUs and SoCs. The ideal candidate will have extensive experience in ASIC design and a strong understanding of circuit design. This role involves validating circuit performance and analyzing timing margins to push the frontiers of computing. Competitive salary offered with a range of $168,000 to $310,500 depending on level and experience.
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