Senior Scale-Up Network System Architect

Define end-to-end system architecture for next-generation NVLink scale-up networks, from link and switch behavior through rack- and pod-level topology. Convert AI training and inference workload needs (LLM, MoE, and emerging model architectures) into specific networking, bandwidth, latency, and resiliency specifications. Drive architecture trade-off studies across performance, cost, power, and reliability, and build the models needed to justify those decisions with data.

Collaborate closely with ASIC, firmware, software, and systems teams to ensure architecture decisions are implementable and land accurately in silicon and product. Develop and use simulation and analytical models to validate architecture choices before committing to silicon. Represent system architecture in multi-functional and customer-facing technical discussions, and serve as a technical expert on scale-up network behavior at scale.

Bachelor's, Master's, or PhD in Computer Science, Computer Engineering, Electrical Engineering, or a related field, or equivalent experience. 8+ years of industry experience in computer networking, system architecture, or high-performance interconnects. Strong grasp of network structure and dynamics at scale, including the impact of topology, congestion, and failure modes on distributed workload performance. Experience developing or using simulation/modeling environments to evaluate architecture trade-offs.

Strong multi-functional collaboration skills - comfortable driving alignment across hardware, firmware, and software teams without direct authority over them. Clear technical communication, including the ability to explain complex architecture trade-offs to both engineering and non-engineering collaborators.

• Direct experience with NVLink, NVSwitch, or comparable scale-up interconnect technologies.
• Hands-on experience with high-performance networking transports such as RoCE (RDMA over Converged Ethernet), including concepts low-latency transport, congestion control, and lossless fabric build.
• Experience with memory subsystem architecture, including memory hierarchies, cache coherency, and memory technologies such as HBM, DDR, or LPDDR.
• Working knowledge of large-scale AI model architectures and how they map to network requirements.
• Background in HPC or supercomputing-scale interconnect development.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 184,000 USD - 287,500 USD for Level 4, and 224,000 USD - 356,500 USD for Level 5. You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until October 8, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal-opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

NVIDIA pioneered accelerated computing. Today, our AI infrastructure powers global intelligence, transforming every industry. Learn more about NVIDIA.