Accelerator Compiler and Tool Chain Lead

We are looking for an Accelerator Compiler Lead to own the compiler andmodel-lowering stack for Velaura’s AI accelerator.

This role will lead the path from customer AI models to optimized executable artifacts for our NPU, including graphimport, operator lowering, compiler IR, graph transformations, quantization integration,code generation, graph partitioning, and compiler diagnostics. The ideal candidate hasbuilt or shipped compiler infrastructure for ML accelerators, GPUs, DSPs, or otherheterogeneous compute targets.

• Lead architecture and development of the AI accelerator compiler stack.
• Own model ingestion and graph lowering from frameworks and exchange formats such as PyTorch export flows, ONNX, Tensor Flow Lite, or similar.
• Define operator coverage strategy, lowering rules, graph transformations, fusion, partitioning, and fallback behavior.
• Develop compiler optimization passes for tensor layout, tiling, memory movement, mixed precision, operator fusion, and hardware-specific scheduling.
• Work closely with accelerator runtime and driver teams to define executable artifact formats, metadata, memory planning requirements, profiling hooks, and runtime constraints.
• Partner with hardware architecture and NPU firmware teams on ISA, command streams, tensor layouts, data movement, hardware constraints, and compiler-visible performance features.
• Own quantization compiler integration, including calibration metadata, precision selection, scale handling, layout constraints, and accuracy/performance tradeoffs.
• Build compiler diagnostics that help customers understand unsupported operators, shape constraints, graph rewrites, quantization issues, and performance bottlenecks.
• Establish compiler verification and regression strategy for graph transformations,IR lowering, numerical behavior, model accuracy, and performance.
• Hire, mentor, and lead a team of compiler and ML systems engineers.

• Deep experience with compiler development, ML graph compilers, or code generation for accelerators, GPUs, DSPs, or heterogeneous compute systems.
• Strong understanding of ML model formats, graph IRs, operator lowering, tensorlayouts, quantization, and runtime/compiler interfaces.
• Strong C++ and Python programming skills and experience buildingproduction-quality compiler or systems software.
• Experience with compiler frameworks or technologies such as MLIR, LLVM,TVM, XLA, IREE, Glow, TensorRT-like systems, OpenVINO-like systems, or equivalent.
• Strong understanding of correctness risks in compiler optimizations, graph rewrites, mixed precision, operator fusion, and hardware-specific lowering.
• Ability to work closely with hardware architects, firmware engineers, runtime engineers, model-integration teams, and SQA.
• Experience leading technical teams or major architecture areas.

• Experience with NPU, GPU, DSP, or AI accelerator compiler stacks.
• Experience with quantization-aware compilation, mixed precision, sparsity, pruning, graph partitioning, or hardware-specific scheduling.
• Experience supporting ONNX, PyTorch export, Tensor Flow Lite, JAX/XLA,Torch Dynamo/Torch Inductor, or other model import flows.
• Familiarity with robotics, computer vision, CNNs, transformers, detection,segmentation, depth, SLAM-adjacent perception, or edge AI workloads.
• Experience building customer-facing compiler diagnostics and model-portingtools.
• Experience with model-zoo release processes, accuracy validation, and reproducible benchmark artifacts.
• Open-source compiler contributions or experience working with externalframework communities.

$200,000 - $300,000 a year

At Velaura, we believe exceptional talent deserves exceptional rewards. Compensation for this role…