Advanced Packaging Engineer

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Eridu AI is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate training and inference for large-scale AI models. Today’s AI performance is frequently limited by system-level bottlenecks. Eridu AI delivers multiple industry-first innovations across semiconductors, software, and systems to unlock greater GPU utilization, reduce capital and power costs, and maximize data center efficiency. The company’s solutions and value proposition have been validated by several leading hyperscalers.

We are seeking an Advanced Packaging Engineer to lead the development, integration, and production enablement of next‑generation multi‑die packaging solutions, including 2.5D CoWoS, bridge‑based, and high‑density chiplet assemblies. This role drives end‑to‑end packaging technology innovation and integration from test vehicle design and early process learning through manufacturing readiness and high‑volume production ramp. The ideal candidate brings deep technical expertise in fine‑pitch interconnects, substrate/interposer technologies, and multi‑die co‑design, coupled with a hands‑on, collaborative approach to working with foundries, OSATs, and system design teams to deliver scalable, high‑performance, and reliable packaging solutions.

• Own test vehicle definition and execution for advanced packaging technologies to drive process learning and technology validation.
• Lead process and material development for advanced flip‑chip and multi‑die assembly flows, achieving optimal performance, yield, and reliability.
• Collaborate with foundries, OSATs, substrate vendors, and system contract manufacturers to ensure material readiness, tooling qualification, BOM completeness, and process maturity from pilot to early production builds.
• Drive system‑level package co‑design in collaboration with silicon floor planning, mechanical, and SI/PI teams to optimize thermal, mechanical, and electrical performance trade‑offs, ensuring manufacturable and reliable solutions.
• Define and execute qualification and reliability test plans, including thermal cycling, warpage control, and mechanical stress evaluations.
• Implement DFM, DFY, DOE, and FMEA methodologies to identify process sensitivities, optimize critical parameters, and drive design/process robustness.
• Lead failure analysis and root cause investigations for yield, reliability, and process excursions, coordinating with FA and design teams for rapid issue resolution and feedback integration.
• Establish design rules, material specifications, and integration guidelines to standardize best practices across programs and suppliers.
• Deliver concise technical reports, risk assessments, and milestone updates to internal and external stakeholders.
• Drive continuous improvement in assembly processes, reliability, and cost/yield performance through data‑driven experiments and supplier engagement.
• Drive and support end‑to‑end productization and system‑level module assembly integration with package partners and contract manufacturers, ensuring seamless technology transition into production.

• Bachelor’s or Master’s degree in Mechanical, Electrical, Materials, or Chemical Engineering (or a related discipline).
• 10+ years of hands‑on experience in advanced IC packaging and multi‑die integration, including 2.5D/3D CoWoS, bridge‑based, or chiplet architectures.
• Proven track record of developing, qualifying, and ramping advanced flip chip packaging technologies from concept to high‑volume manufacturing.
• Strong understanding of substrate technologies, including materials, manufacturing rules, roadmaps, and design‑for‑cost/yield trade‑offs.
• Experience collaborating with foundries, OSATs, system CM, and substrate vendors on technology enablement, fine‑pitch assembly, and reliability validation.
• Knowledge of assembly and substrate material properties, metallurgy, and their behavior under thermal, mechanical, and environmental use conditions.
• Strong understanding of advanced packaging technology trends and roadmaps with silicon foundry and OSAT partners.
• Working knowledge of…