Physical Design Engineer

We are a stealth‑mode startup in Silicon Valley focused on high‑performance, low‑power RISC‑V processor design. Our experienced microprocessor design team seeks highly motivated individuals to work on cutting‑edge processor design in a small, collaborative environment.

Job Description

As a Physical Design Engineer, you will join an innovative single‑ and multiport SRAM technology development effort. Your responsibilities include creating and maintaining Aril patented SRAM macros, generating all required leaf‑cell views (LEF, Abstract, .lib, etc.), collaborating with circuit designers to understand cell operation, verifying layout with DRC/LVS tools, and establishing power/gnd and psub/nwell tap grids for larger macros.

• Circuit simulation and characterization of leaf cells using Liberty/Viola/etc.
• Develop and maintain structured routing of memory macros
• Collaborate with IP teams to ensure validity, completeness, and usability of collateral (LIB/LEF, etc.)
• Participate in all SOC‑level sign‑off checks and generate final GDSII for delivery to the foundry.

• BS in Electrical Engineering + 7 years of combined physical and circuit design experience
• Tape‑out experience in advanced technology nodes (5nm or below)
• Experience with CTS of high‑speed clocks (3GHz+)
• Strong coding skills and experience scripting for cross‑team use
• Programming proficiency in TCL
• Familiarity with tools such as Innovus, Pegasus/ICV, Prime Time/Tempus, Voltus, Viola/Liberty
• Excellent teamwork, innovative mindset, self‑directed and strong communication skills
• Thrives in a small startup team environment

Mid‑Senior Level

Full‑time

Engineering and Information Technology

Location: Sunnyvale, CA Salary: $‑$ US