RTL Networking ASIC Engineer – Latency & QoS Focus

A leading semiconductor company in Saratoga is looking for an experienced RTL Engineer specializing in Networking ASIC design. The role involves defining and implementing cutting-edge networking chips, with a focus on performance optimization, protocol support, and troubleshooting. Ideal candidates should have a master's degree and significant experience in ASIC design, along with expertise in System Verilog and Verilog. The compensation ranges from $210,000 to $275,000 annually, depending on qualifications and experience.
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