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Senior RTL Packet Buffering Engineer Speed Networking

Job in Saratoga, Santa Clara County, California, 95071, USA
Listing for: Eridu
Full Time position
Listed on 2026-01-01
Job specializations:
  • Engineering
    Hardware Engineer, Systems Engineer
Salary/Wage Range or Industry Benchmark: 210000 - 275000 USD Yearly USD 210000.00 275000.00 YEAR
Job Description & How to Apply Below
Position: Senior RTL Packet Buffering Engineer – High‑Speed Networking
A Silicon Valley hardware startup is looking for an RTL Packet Buffering engineer to define and implement cutting-edge Networking IC. In this full-time role, you will design solutions for networking chips, ensuring high performance and compliance with industry standards. Candidates must have a ME/BE and 8-15 years of experience, along with proficiency in System Verilog and networking protocols. This position offers a salary range of $210,000 – $275,000 based on qualifications and experience.
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Position Requirements
10+ Years work experience
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