ASIC Design Verification Lead

Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI . Today’s AI performance is frequently limited by communication bottlenecks. Eridu delivers multiple industry-first innovations across silicon, packaging, software, and systems to deliver a step function in AI networking – a network switch that is an order of magnitude improvement in bandwidth and radix versus today’s "state of the art" switches.

This is the first silicon and system designed from the ground up for AI and the increase in radix and throughput unlocks greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs, improving reliability, simplifying operations and speeding AI data center deployments for faster time to revenue.

The company’s solutions and value proposition have been widely validated by leading hyperscalers.

The company has raised $200M to date including its most recent, oversubscribed Series A round led by Socratic Partners, John Doerr, Hudson River Trading, Capricorn Investment Group and Matter Venture Partners, with participation by SBVA, Media Tek, Bosch Ventures, TDK Ventures, Eclipse Ventures, and Venture Tech Alliance, among others.

Eridu is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exists, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the- art silicon, packaging, optics, software, and systems.

Eridu has also assembled a world class IP, design and manufacturing ecosystem to execute on its vision, and counts TSMC as a key partner in our journey.

Visit our website eridu.ai to learn more.

We are seeking a hands-on ASIC Design Verification Lead to own verification execution for complex, high-performance networking silicon. This role is a senior technical leadership position focused on driving verification strategy, infrastructure, and closure, while remaining deeply involved in day-to-day hands-on verification work.

This is not a people-manager-only role. The ideal candidate is a highly technical verification leader who has personally taken chips to tape-out, understands how verification breaks late in the cycle, and can drive functional correctness, coverage closure, and tape-out readiness in a fast-moving startup environment.

• Define and own block-, subsystem-, and chip-level verification strategies
• Develop and maintain scalable verification environments using System Verilog and UVM
• Drive execution from test-plan definition through coverage and bug closure
• Ensure verification readiness as a gating requirement for tape-out
• Write and review high-quality test benches, sequences, checkers, and scoreboards
• Develop constrained-random, directed, and stress tests to validate complex corner cases
• Actively debug functional failures across RTL, testbench, and simulation environments

Coverage & Quality Ownership

• Define functional, code, and assertion coverage goals
• Analyze coverage results and identify verification gaps
• Provide clear, actionable feedback to RTL designers to improve design and test quality

Cross-Functional Debug & Collaboration

• Partner closely with RTL, architecture, physical design, and firmware teams
• Drive root-cause analysis of functional, performance, and integration issues
• Support gate-level, timing-aware, and…