Senior Substrate Design Layout Engineer

Piper Companies is seeking a Senior Substrate Design Layout Engineer to support an industry‑leading semiconductor organization for a permanent
, onsite opportunity based in Saratoga, CA
. The Senior Substrate Design Layout Engineer will contribute to the development and layout of cutting‑edge organic substrate solutions for next‑generation multi‑die and chiplet computing platforms.

• Lead detailed layout activities for complex organic substrates, including bump planning, routing schemes, and multilayer stack‑up development.
• Define routing and power‑delivery strategies that support high‑speed interfaces and high‑current architectures across advanced package substrates.
• Collaborate closely with integration, silicon, SI/PI, and mechanical teams to ensure cohesive co‑design and layout feasibility.
• Evaluate design risks early in development and recommend layout‑driven improvements to meet electrical, mechanical, and manufacturability constraints.
• Interface with substrate suppliers and OSAT partners to validate design readiness, manufacturability, and overall yield performance.

• 10+ years of experience in advanced organic substrate design or high‑performance IC package layout.
• Background working with multi‑die, chiplet, or high‑density module architectures using ABF and multilayer organic technologies.
• Proficiency in Siemens Xpedition (preferred) and experience with tools such as Cadence Allegro/APD.
• Hands‑on experience collaborating with OSATs and global substrate vendors, including driving designs through tape‑out.
• Strong understanding of SI/PI concepts, HDI structures, and routing practices supporting high‑speed signals and advanced power delivery networks.

Salary Range: $235,000-$265,000/year (USD)

Comprehensive Benefits:
Medical, Dental, Vision, sick leave if required by law, and 401K

‑die modules, ABF substrates, Siemens Xpedition, Allegro APD, OSAT, HDI routing, SI/PI, high‑speed interfaces, power delivery networks, PCB layout, co‑design, semiconductor packaging, bump planning, escape routing, stack‑up design, manufacturability, high‑density routing, tape‑out.