Lead ASIC Chip Design Expert Chip Tapeout

Position: Lead ASIC Chip Design Expert — Full-Chip Tapeout
A Silicon Valley hardware startup is seeking an ASIC Chip Design Lead to drive chip design execution from micro-architecture through full-chip integration. This technical role requires hands-on RTL development, managing cross-functional design teams, and ensuring timing closure for full-chip designs. Ideal candidates will have extensive experience in RTL design, micro-architecture, and a proven track record of successful full-chip tape-outs, making impactful contributions to AI infrastructure technology.
The Lead ASIC Chip Design Expert — Full-Chip Tapeout role at Eridu Corporation is now open for applications in Saratoga, CA, United States. We invite applications for the Lead ASIC Chip Design Expert — Full-Chip Tapeout position located in Saratoga, CA, United States. The following opening is for a Lead ASIC Chip Design Expert — Full-Chip Tapeout with Eridu Corporation.

Our team is growing, and we are hiring a Lead ASIC Chip Design Expert — Full-Chip Tapeout in Saratoga, CA, United States.