Senior RTL Design Engineer - ASIC, SystemVerilog & QoS
Listed on 2026-11-04
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Engineering
Electronics Engineer, Hardware Engineer, Test Engineer
Inter Sources Inc. is seeking a senior engineer with 8–15 years of ME/BE experience to design and optimize ASIC-related systems.
The role requires hands-on System Verilog/Verilog, in-depth knowledge of ASIC methodologies, and strong analytical skills for debugging complex networking issues. The candidate should be proficient in enabling high-performance scheduling and QoS mechanisms, with experience in Ethernet and IP protocols and a proven ability to communicate effectively within
We are seeking a motivated Senior RTL Design Engineer - ASIC, System Verilog & QoS to join Inter Sources Inc in Saratoga, CA, United States.
We would love to welcome a new Senior RTL Design Engineer - ASIC, System Verilog & QoS to our team in Saratoga, CA, United States.
For the Senior RTL Design Engineer - ASIC, System Verilog & QoS position at Inter Sources Inc, we are reviewing applications now.
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